Next TTA: High-Confidence Architecture for Distributed Control Applications

IST Programme RTD Research Project IST-2001-32111

Project Description

The NEXT TTA project enhances the structure, functionality and dependability of the time-triggered architecture (TTA) to meet the austere cost structure of the automotive industry, while satisfying the rigourous safety requirements of the aerospace industry. By placing the safety-relevant algorithms, that are formally analyzed, into intelligent replicated star couplers, NEXT TTA reduces the cost and generalizes the failure assumptions of the node computers. Event-triggered communication services are integrated into the TTA to increase the required flexibility. The synchronous programming environment LUSTRE and its toll set are extended for the TTA and automated worst-case-execution-time analysis is explored. CORBA compliant interfaces are provided in order to make TTA systems interoperable with the open information infrastructure. The limits of implementing the TTA with COTS components in the gigabit range are investigated. Research at Ulm focuses on the application of formal methods to Next-TTA. The specification and verification system PVS is used to formally analyse the most critical algorithms of TTA. For more information on Next-TTA see the Next-TTA Homepage at the University of Vienna.

Group Members

• F. W. von Henke
• H. Pfeifer

Project Partners

• Technische Universität Wien
• Austriamicrosystems AG
• Audi AG
• Budapest University of Technology and Economics
• Chalmers University of Technology
• TTTech Computertechnik AG
• Université Joseph Fourier
• Centre National de la Recherche Scientifique
• Institut National Polytechnique de Grenoble
• University of York

Publications

• H. Pfeifer, F. von Henke
  Modular Formal Analysis of the Central Guardian in the Time-Triggered Architecture
  23rd International Conference on Computer Safety, Reliability and Security (SAFECOMP)
  Potsdam, Germany, September 21-24, 2004
  

• W. Steiner, J. Rushby, M. Sorea, H. Pfeifer
  Model Checking a Fault-Tolerant Startup Algorithm:
  From Design Exploration To Exhaustive Fault Simulation
  Proc. of DSN 2004, pp. 189-198, June/July 2004

• H. Pfeifer
  Formal Analysis of Fault-Tolerant Algorithms in the Time-Triggered Architecture
  PhD Thesis, Univ. Ulm, 2003